Summary: IEEE Instrumentation and Measurement
Technology Conference
Lake Como, Italy, May 18­20, 2004
Test Methodology for Low Power VLSI Neural Oscillator Circuit
Young Jun Lee, Jihyun Lee, Jaeyoung Heo, Fengming Zhang, Yong Bin Kim, F. Lombardi
ECE Department,
Northeastern University,
Boston MA 02115, USA
E­mail: yjlee, jlee, jheo, fzhang, ybk, lombardi @ece.neu.edu
Abstract ­ This paper presents new test and verification methodologies, in-
cluding design techniques targeting a neural oscillator. Because the output
signal of a neuron is chaotic, customized verification and test methodologies
are required. We have chosen to use MATLAB to verify our experimental re-
sults at a simulation level. In this paper we also describe a test circuit used
to perform electronic neuron IC testing. We investigate how a subthreshold
circuit can reduce power consumption. In our HSPICE simulations, we both
validate the proposed test circuit and verify the electronic neuron and synapse
circuit.
Keywords ­ test methodology, chaotic, electronic neuron, chemical synapse,
subthreshold, tanh, comparator

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

Collections: Engineering