Summary: IEEE International Symposium on Circuits and Systems (ISCAS'98), 31 May -- 3 June 1998, Monterey, CA, pp. D441­D444.
DATA BLOCK PROCESSING FOR LOW POWER IMPLEMENTATION OF DIRECT FORM FIR FILTERS ON
SINGLE MULTIPLIER CMOS DSPs
T. Arslan and A.T. Erdogan
Cardiff University of Wales
Cardiff School of Engineering, PO Box 689,
Cardiff CF2 3TF,
United Kingdom
ARSLAN@Cardiff.ac.uk, ERDOGAN@Cardiff.ac.uk
ABSTRACT
In this paper, the authors propose a block processing
scheme for low power implementation of FIR filters on
single multiplier CMOS based Digital Signal Processors
(DSPs). The authors show that the reduction in overall
power is due to a decrease in switching activity at
coefficient inputs of the multiplier and both data and
coefficient memory buses by a factor determined by the
data input block size. Results are presented which
demonstrate up to 34% savings in power. The paper
presents the scheme, outlines its implementation using an

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

Collections: Engineering