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Compiler Support for Scalable and Efficient Memory Rajeev Barua y , Walter Lee z , Saman Amarasinghe z , Anant Agarwal z \Lambda
 

Summary: Compiler Support for Scalable and Efficient Memory
Systems
Rajeev Barua y , Walter Lee z , Saman Amarasinghe z , Anant Agarwal z \Lambda
ECE Department; University of Maryland y
College Park, MD 20742, U.S.A
barua@eng,umd.edu
http://www.ece.umd.edu/~barua
M:I:T: Laboratory for Computer Science z
Cambridge, MA 02139, U.S.A.
fwalt,saman,agarwalg@lcs.mit.edu
http://www.cag.lcs.mit.edu/raw
Abstract
Technological trends require that future scalable microprocessors be decentralized. Applying
these trends toward memory systems shows that size of cache accessible in a single cycle will
decrease in future generation of chips. Thus, a bank­exposed memory system comprising of small,
decentralized cache banks must eventually replace that of a monolithic cache. This paper considers
how to effectively use such a memory system for sequential programs.
This paper presents Maps, the software technology central to bank­exposed architectures, which
are architectures with bank­exposed memory systems. Maps solves the problem of bank disam­
biguation -- that of determining at compile­time which bank a memory reference is accessing. Bank

  

Source: Amarasinghe, Saman - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Department of Electrical Engineering and Computer Science, RAW Project

 

Collections: Computer Technologies and Information Sciences