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Embedded Reconfigurable Array Fabrics for Efficient Implementation of Image Compression Techniques
 

Summary: Embedded Reconfigurable Array Fabrics for Efficient
Implementation of Image Compression Techniques
Sajid Baloch1,2
, Tughrul Arslan1,2
, Adrian Stoica1,3
1: School of Electronics & Engineering. University of Edinburgh, King's Buildings, Mayfield Rd, EH9 3JL, UK
2: Institute for System Level Integration, The Alba Campus, The Alba Centre, Livingston, EH54 7EG, UK)
3: NASA, Jet Propulsion Laboratory, 4800 Oak Grove Drive, Pasadena, CA 91109, USA
ABSTRACT
The discrete wavelet Transform (DWT), as
defined by the Image Compression Standard
JPEG-2000, is one of the most time-consuming
computations which cannot be efficiently executed
on current hardware architectures. This paper
presents and compares a number of new, different
architectures for domain-specific arrays to
efficiently implement various DWT algorithms. A
number of different algorithms are mapped to
demonstrate the flexibility of these new embedded
configurable SoC architectures and their ability to

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering