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New SRAM Cell Design for Low Power and High Reliability using 32nm Independent Gate FinFET Technology
 

Summary: New SRAM Cell Design for Low Power and High Reliability using 32nm
Independent Gate FinFET Technology
Young Bok Kim
Dept. of Electrical and
Computer Engineering
Northeastern University
youngbok@ece.neu.edu
Yong-Bin Kim
Dept. of Electrical and
Computer Engineering
Northeastern University
ybk@ece.neu.edu
Fabrizio Lombardi
Dept. of Electrical and
Computer Engineering
Northeastern University
lombardi@ece.neu.edu
Abstract
This paper proposes new methods for SRAM cell
design in FinFET technology. One of the most

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering