Summary: A Customized MVA Model for ILP Multiprocessors \Lambda
Daniel J. Sorin y , Mary K. Vernon y , Vijay S. Pai z , Sarita V. Adve z , and David A. Wood y
y Computer Sciences Dept z Dept of Electrical & Computer Engineering
University of Wisconsin ­ Madison Rice University
fsorin, vernon, davidg@cs.wisc.edu fvijaypai, saritag@rice.edu
University of Wisconsin­Madison Computer Sciences Technical Report #1369.
Rice University Electrical and Computer Engineering Technical Report #9803.
Abstract
This paper provides the customized MVA equations for an analytical model for evaluating architectural alternatives for
shared­memory multiprocessors with processors that aggressively exploit instruction­level parallelism (ILP). Compared to
simulation, the analytical model is many orders of magnitude faster to solve, yielding highly accurate system performance
estimates in seconds.
1 Introduction
In [8], we presented an analytical model for evaluating specific types of architectural trade­offs for shared­memory systems
with ILP processors. As shown in that paper, the analytical model validates extremely well against detailed simulation and
produces results in a few seconds.
The principal aspects of the model are:
ffl The ILP processor and its associated two­level cache system are viewed as a black box that generates requests to the
memory system and intermittently blocks after a dynamically changing number of requests.
ffl We iterate between two submodels; one represents the blocking behavior due to load misses that cannot be retired until

Source: Adve, Sarita - Department of Computer Science, University of Illinois at Urbana-Champaign

Collections: Computer Technologies and Information Sciences