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J Supercomput (2008) 45: 341364 DOI 10.1007/s11227-008-0178-0
 

Summary: J Supercomput (2008) 45: 341­364
DOI 10.1007/s11227-008-0178-0
An energy consumption characterization of on-chip
interconnection networks for tiled CMP architectures
Antonio Flores · Juan L. Aragón ·
Manuel E. Acacio
Published online: 13 February 2008
© Springer Science+Business Media, LLC 2008
Abstract Continuous improvements in integration scale have made possible the in-
clusion of several processor cores on the same chip. Such designs have been named
chip-multiprocessors (or CMPs) and constitute a good alternative to traditional mono-
lithic designs for several reasons, among others, better levels of performance, scala-
bility, and performance/energy ratio. On the other hand, higher clock frequencies and
increasing number of transistors available on a single chip have revealed energy con-
sumption as a critical design issue in current and future microarchitectures. In these
architectures, the design of the on-chip interconnection network has proven to have
significant impact on overall system performance and energy consumption, and that
the wires used in such interconnect can be designed with varying latency, bandwidth,
and power characteristics.
In this work, we present a detailed characterization of the energy-efficiency

  

Source: Acacio, Manuel - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia
Aragón Alcaraz, Juan Luis - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia

 

Collections: Computer Technologies and Information Sciences