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H.264 Decoder Implementation on a Dynamically Reconfigurable Instruction Cell Based Architecture
 

Summary: H.264 Decoder Implementation on a Dynamically Reconfigurable
Instruction Cell Based Architecture
Adam Major, Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawam and Tughrul Arslan
School of Engineering and Electronics
University of Edinburgh, Edinburgh, EH9 3JL
Tel: (+44)131 650 5619 Email: adam.major@ed.ac.uk
ABSTRACT
This paper presents a new Baseline Profile
compliant h.264 decoder implementation specifically
tailored for an ANSI-C programmable, dynamically
reconfigurable, instruction cell based architecture
which has recently been developed [10]. We use the
ffmpeg libavcodec library as the basis for our
decoder and identify the most processor intensive
functions. These functions are tailored in a novel
framework incorporating established software
techniques alongside several architecture specific
transforms. Initial results demonstrate that our
reconfigurable architecture based decoder provides
a significant performance boost with power figures

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering