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Maps: A CompilerManaged Memory System for Raw Machines Rajeev Barua, Walter Lee, Saman Amarasinghe, Anant Agarwal
 

Summary: Maps: A Compiler­Managed Memory System for Raw Machines
Rajeev Barua, Walter Lee, Saman Amarasinghe, Anant Agarwal
M.I.T. Laboratory for Computer Science
Cambridge, MA 02139, U.S.A.
fbarua,walt,saman,agarwalg@lcs.mit.edu
http://cag­www.lcs.mit.edu/raw
Abstract
This paper describes Maps, a compiler managed memory
system for Raw architectures. Traditional processors for
sequential programs maintain the abstraction of a unified
memory by using a single centralized memory system. This
implementation leads to the infamous ``Von Neumann bottle­
neck,'' with machine performance limited by the large mem­
ory latency and limited memory bandwidth. A Raw archi­
tecture addresses this problem by taking advantage of the
rapidly increasing transistor budget to move much of its
memory on chip. To remove the bottleneck and complex­
ity associated with centralized memory, Raw distributes the
memory with its processing elements. Unified memory se­
mantics are implemented jointly by the hardware and the

  

Source: Amarasinghe, Saman - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)

 

Collections: Computer Technologies and Information Sciences