Summary: Generalized Tardiness Bounds for Global Multiprocessor
James H. Anderson
Department of Computer Science, The University of North Carolina at Chapel Hill
We consider the issue of deadline tardiness under global multiprocessor scheduling algo-
rithms. We present a general tardiness-bound derivation that is applicable to a wide variety of
such algorithms (including some whose tardiness behavior has not been analyzed before). Our
derivation is very general: job priorities may change rather arbitrarily at runtime, capacity restric-
tions may exist on certain processors, and, under certain conditions, non-preemptive regions are
allowed. Our results show that, with the exception of static-priority algorithms, most global al-
gorithms considered previously have bounded tardiness. In addition, our results provide a simple
means for checking whether tardiness is bounded under newly-developed algorithms.
Most major chip manufacturers are investing in multicore technologies to continue performance im-
provements in their product lines in the face of fundamental limitations of single-core chip designs.
To date, several manufacturers have released dual-core chips, Intel and AMD each have quad-core
chips on the market, and Sun's Niagara and more recent Niagara 2 systems have eight-core chips
with multiple hardware threads per core. In the future, per-chip core counts are expected to increase