Summary: CORDIC­Based MMSE­DFE Coefficient Computation
Naofal Al­Dhahir \Lambda and Ali H. Sayed y
Abstract
A modular parallel architecture for a MMSE--DFE coefficient computation processor is
presented. The architecture is based on QR factorization of a channel--and--noise--dependent
data matrix and is implemented using CORDIC processors within a systolic array architecture.
Implementation issues including the number of CORDIC stages and the bit precision required
in a fixed--point implementation are investigated through computer simulations. The proposed
architecture accommodates fractionally--spaced DFEs, co--channel interference, and multiple
diversity paths.
1 Introduction
In many wireless packet data communication systems, a training sequence is embedded in each
packet and used at the receiver to estimate the channel impulse response (CIR). The CIR estimate
is then used to compute the optimal equalizer settings or the branch metrics of a maximum likelihood
sequence estimator (MLSE) to mitigate inter­symbol interference (ISI) and noise.
On severe­ISI channels, such as those encountered in GSM--based digital cellular systems and the
emerging broadband wireless services, the mean­square--error decision feedback equalizer (MMSE­
DFE) has been demonstrated to be a high­performance receiver structure [4, 11, 12] and can have
a much lower complexity than MLSE receivers (whose complexity grows exponentially with the
channel delay spread). In particular, a channel­estimate­based MMSE­DFE has been shown to

Source: Al-Dhahir, Naofal - Department of Electrical Engineering, University of Texas at Dallas

Collections: Engineering