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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004 2467 A 2.5-V 14-bit 61 CMOS SOI
 

Summary: IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004 2467
A 2.5-V 14-bit 61 CMOS SOI
Capacitive Accelerometer
Babak Vakili Amini, Student Member, IEEE, and Farrokh Ayazi, Member, IEEE
Abstract--This paper presents a 2.5-V 14-bit fully differen-
tial 61 interface circuit in 0.25- m CMOS technology for a
high-resolution silicon-on-insulator capacitive accelerometer fab-
ricated using a simple CMOS-compatible stictionless process. The
integrated circuit is based on programmable front-end back-end
first-order 61 architecture and provides a 1-bit pulse-width
modulated digital output. Using correlated double sampling, the
low-frequency noise is suppressed by 10 dB. Capacitive resolu-
tion is 22 aF at 75 Hz (resolution bandwidth =1 Hz), equivalent
to 110 g with a dynamic range of 85 dB (14-bit resolution)
and a sensitivity of 500 mV/g. The chip occupies 2 mm2 and
consumes 6 mW.
Index Terms--CMOS SOI capacitive accelerometers, correlated
double sampling (CDS), MEMS interface circuit, programmable
switched-capacitor amplifier, sigma-delta modulator.
I. INTRODUCTION

  

Source: Ayazi, Farrokh - School of Electrical and Computer Engineering, Georgia Institute of Technology

 

Collections: Engineering