Summary: To appear in the Proceedings of the 36th
Annual International Symposium on Microarchitecture (MICRO), December 2003
Single-event upsets from particle strikes have become a
key challenge in microprocessor design. Techniques to
deal with these transient faults exist, but come at a cost.
Designers clearly require accurate estimates of processor
error rates to make appropriate cost/reliability trade-offs.
This paper describes a method for generating these
A key aspect of this analysis is that some single-bit faults
(such as those occurring in the branch predictor) will not
produce an error in a program's output. We define a
structure's architectural vulnerability factor (AVF) as the
probability that a fault in that particular structure will
result in an error. A structure's error rate is the product of
its raw error rate, as determined by process and circuit
technology, and the AVF.
Unfortunately, computing AVFs of complex structures,