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Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous
 

Summary: Efficient Message Management in Tiled CMP
Architectures Using a Heterogeneous
Interconnection Network
Antonio Flores, Juan L. Arag´on, and Manuel E. Acacio
Departamento de Ingenier´ia y Tecnolog´ia de Computadores
University of Murcia, 30100 Murcia (Spain)
{aflores, jlaragon, meacacio}@ditec.um.es
Abstract. Previous studies have shown that the interconnection network
of a Chip-Multiprocessor (CMP) has significant impact on both overall
performance and energy consumption. Moreover, wires used in such in-
terconnect can be designed with varying latency, bandwidth and power
characteristics. In this work, we present a proposal for performance-and
energy-efficient message management in tiled CMPs by using a heteroge-
neous interconnect. Our proposal consists of Reply Partitioning, a tech-
nique that classifies all coherence messages into critical and short, and
non-critical and long messages; and the use of a heterogeneous intercon-
nection network comprised of low-latency wires for critical messages and
low-energy wires for non-critical ones. Through detailed simulations of 8-
and 16-core CMPs, we show that our proposal obtains average improve-
ments of 8% in execution time and 65% in the Energy-Delay2

  

Source: Acacio, Manuel - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia

 

Collections: Computer Technologies and Information Sciences