Summary: Simultaneous Routing and Buffer Insertion with Restrictions on Buffer
Locations \Lambda
Hai Zhou 1 , D.F. Wong 1 , I­Min Liu 2 , and Adnan Aziz 2
1 Department of Computer Sciences, University of Texas, Austin, TX 78712
2 Department of Electrical and Computer Engineering, University of Texas, Austin, TX 78712
Abstract
During the routing of global interconnects, macro blocks form
useful routing regions which allow wires to go through but for­
bid buffers to be inserted. They give restrictions on buffer
locations. In this paper, we take these buffer location re­
strictions into consideration and solve the simultaneous maze
routing and buffer insertion problem. Given a block place­
ment defining buffer location restrictions and a pair of pins
(a source and a sink), we give a polynomial time exact algo­
rithm to find a buffered route from the source to the sink with
minimum Elmore delay.
1 Introduction
With the evolution of VLSI fabrication technology, intercon­
nect delay, especially global interconnect delay, has become
the dominant factor in deep sub­micron design. Many

Source: Aziz, Adnan - Department of Electrical and Computer Engineering, University of Texas at Austin
Zhou, Hai - Department of Electrical and Computer Engineering, Northwestern University

Collections: Computer Technologies and Information Sciences