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Summary: AN EFFICIENT RECTILINEAR STEINER TREE ALGORITHM FOR VLSI GLOBAL
ROUTING
Shawki Areibi
School of Engineering
University of Guelph
CANADA N1G 2W1
E-mail: sareibi@uoguelph.ca
Min Xie and Anthony Vannelli
Electrical Engineering Dept
University of Waterloo
CANADA N2L 2G1
E-mail: vannelli@cheetah.vlsi.uwaterloo.ca
ABSTRACT
As we move to deep sub-micron designs below 0.18 mi-
crons, the delay of a circuit, as well as power dissipation
and area, is dominated by interconnections between logical
elements (i.e. transistors)[1]. The focus of this paper is on
the global routingproblem. Both global and channel routing
are NP-hard[2]; therefore, all existing solution methodolo-
gies are heuristics. The main aim is to develop an efficient
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