Summary: An accurate performance model of shared buffer ATM switches under
hot spot traffic
, M. Atiquzzamanb,*
School of Computer Science and Computer Engineering, La Trobe University, Melbourne 3083, Australia
Department of Electrical and Computer Engineering, University of Dayton, Dayton, OH 45469-0226, USA
Received 12 August 1998; received in revised form 1 December 1998; accepted 1 December 1998
Asynchronous transfer mode (ATM) switches based on shared buffering are known to have better performance and buffer utilization than
input or output queued switches. Shared buffer switches do not suffer from head of line blocking which is a problem in simple input buffering.
Shared buffer switches have previously been studied under uniform and unbalanced traffic patterns. However, due to the complexity of the
model, the performance of such a switch, in the presence of a single hot spot, has not been fully explored. In this article, we develop a model
for a multistage ATM switch constructed of shared buffer switching elements and operating under a hot spot traffic pattern. The model is used
to study the switch performance in terms of the throughput, cell delay, cell loss probability and the optimal buffer size. 1999 Elsevier
Science B.V. All rights reserved.
Keywords: Asynchronous transfer mode; Broadband ISDN; Switching elements; Performance evaluation; High speed networks
In the recent years, Broadband ISDN (B-ISDN) has