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A CMOS Delayed Locked Loop (DLL) for Reducing Clock Skew to Under 500ps
 

Summary: A CMOS Delayed Locked Loop (DLL) for Reducing Clock Skew to
Under 500ps
Element
Phase detector
Charge pump
Delav line
Yong-Bin Kim
Department of Electrical Engineering
Area(sq.pm)
8,800
30,800
4.400
Abstract
Thas paper presents a varaable delay lane DLL car-
cuat amplemented an a 0.8 p m CMOS technology. A
phase detector and two charge pump carcuats calabrate
the delay per stage of the delay lane usang push-pull
type clock synchronazataon scheme. The delay lane can
be programmed 6 to 18 stages. The DLL carcuat as ca-
pable of reducang clock skew from 1-3ns to below 500ps

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering