Home

About

Advanced Search

Browse by Discipline

Scientific Societies

E-print Alerts

Add E-prints

E-print Network
FAQHELPSITE MAPCONTACT US


  Advanced Search  

 
900 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 5, MAY 2011 A 11-Transistor Nanoscale CMOS Memory Cell for
 

Summary: 900 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 5, MAY 2011
A 11-Transistor Nanoscale CMOS Memory Cell for
Hardening to Soft Errors
Sheng Lin, Yong-Bin Kim, and Fabrizio Lombardi
Abstract--This paper proposes a new hardening design for an 11 transis-
tors (11T) CMOS memory cell at 32 nm feature size. The proposed hard-
ened memory cell overcomes the problems associated with the previous de-
sign by utilizing novel access and refreshing mechanisms. Simulation shows
that the data stored in the proposed hardened memory cell does not change
even for a transient pulse of more than twice the charge than a conventional
memory cell. Moreover it achieves 55% reduction in power delay product
compared to the DICE cell (with 12 transistors) providing a significant im-
provement in soft error tolerance. Simulation results are provided using
the predictive technology file for 32 nm feature size in CMOS.
Index Terms--Memory design, nanotechnology, radiation hardening.
I. INTRODUCTION
The tremendous scaling of CMOS technology necessitates reliable
operation for many circuit designs. Due to the lower Vdd and the
smaller node capacitance, the amount of charge stored on a circuit
node is becoming increasingly smaller, thus making circuits more

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering