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A Novel Low-Power Reconfigurable FFT Processor Yutian Zhao1

Summary: A Novel Low-Power Reconfigurable FFT Processor
Yutian Zhao1
, Ahmet T. Erdogan1,2
and Tughrul Arslan1,2
University of Edinburgh, School of Engineering and Electronics
Edinburgh, EH9 3JL, Scotland, United Kingdom
Institute for System Level Integration, The ALBA Campus
Livingston, EH54 7EG, Scotland, United Kingdom
Y.Zhao@ed.ac.uk, Ahmet.Erdogan@ee.ed.ac.uk, Tughrul.Arslan@ee.ed.ac.uk
Abstract--A novel low-power reconfigurable FFT processor is
proposed in this paper. The architecture is served as a scalable
IP Core which is suitable for System on Chip applications. The
system can be configured as from 16-point to 1024-point FFT.
Flexibility is added to address generation block, coefficient
memory block and data memory block. Two switch blocks are
implemented to route data and addresses to the right memory
blocks. Compared with a conventional ASIC FFT processor,
this FFT processor is characterized by having reconfigurability;


Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh


Collections: Engineering