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Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations
 

Summary: Load Board Designs Using Compound Dot Technique and Phase
Detector for Hierarchical ATE Calibrations
Fengming Zhang, Warren Necoechea, Peter Reiter, Yong-Bin Kim*, Fabrizio
Lombardi*
LTX Corporation, Northeastern University*
{Fengming_Zhang, Warren_Necoechea, Peter_Reiter}@ltx.com
{ybk,Lombardi}@ece.neu.edu
Abstract
This paper presents two load board designs for hierarchical calibration of largely
populated ATE. Compound dot technique and phase detector are used on both boards to
provide automatic and low cost calibration of ATE with or without a single reference clock.
Two different relay tree structures are implemented on the two boards with advanced board
design techniques for group offset calibration. Various error sources have been identified and
analyzed on both boards based on SPICE simulations and real measurements. TDR
measurement compares the two approaches and shows that the two load boards give a
maximum of 37ps group timing skew and can be calibrated out by the calibration software.
1. Introduction
Today's IC test systems have achieved 1024 tester pins per testhead in Gigahertz frequency,
and more pins will be available in near future. This brings a challenging calibration problem
of aligning all the pins to the same drive edge and the compare edge. It is impossible,

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering