This paper introduces two new methods for observing
and recording the vectors that have been asserted on a bus.
The first is a software approach that uses a novel data
structure similar to binary decision diagrams which allows
for a compact representation of stored values. Even though
the new data structure presented in this paper can poten-
tially grow to contain just as many nodes as there are pos-
sible values, such cases are often rare. The second is a
hardware approach that is based on a simple circuit con-
sisting of a small memory and two counters and has the
ability to perform at the speed of the microprocessor.
Keywords: Design validation, bus monitoring,
microprocessor verification, post-silicon debug.
As microprocessor continue to grow in complexity,
the visibility to the internal state is adversely affected,
making it increasingly difficult to attain critical
debugging information. Methods such as JTAG and
sample-on-the-fly  can be used to alleviate this