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Summary: Abstract
Multiple Input - Multiple Output (MIMO) wireless
technology involves highly complex vectors and matrix
computations which are directly related to increased
power and area consumption. This paper proposes an
area and power efficient VLSI architecture that can
serve the dual purpose of minimum norm sorting of
rows as well as upper/lower block tri-angularization of
matrices. The resources inside the architecture are
shared among both operations and only primitive
computations are used. Results indicate saving in silicon
real estate as well as power consumption compared to
previous architecture without degrading performance.
1. Introduction
Multiple Input - Multiple Output (MIMO) wireless
communication promises to remove the limits of wireless
networks by providing spectral efficiency near Shannon's
bound [1]. Because of its benefits, MIMO is entering into
almost every wireless standard such as 802.11n for Wi-Fi
and 802.16 for WiMax application. MIMO involves
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