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System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Ali Ahmadinia, Balal Ahmad, Tughrul Arslan
 

Summary: System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip
Design
Ali Ahmadinia, Balal Ahmad, Tughrul Arslan
The University of Edinburgh
School of Engineering and Electronics
Mayfield Road, EH9 3JL Edinburgh, Scotland
{A.Ahmadinia, B.Ahmad, T.Arslan}@ed.ac.uk
Abstract
In the system-on-chip (SoC) era, the growing number of
functionalities included on a single chip requires the de-
velopment of new design methodologies to keep the design
complexity under control. Intellectual property reuse has
been commonly employed as a technique to address this
problem, but a new system-level approach is needed to in-
tegrate IP-Reuse methodology in the design flow, in order
to speed up the designer's productivity. This paper aims to
produce new high level IP models in SystemC for functional
verification of IP integrations, incorporating both embed-
ded custom reconfigurable and conventional IPs, which are
optimised in terms of IP Core parameters. As a case study,

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering