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Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration
 

Summary: Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through
On-Chip Directory Integration
Manuel E. Acacio, Jos´e Gonz´alez, Jos´e M. Garc´ia
Dpto. Ing. y Tecnolog´ia de Computadores
Universidad de Murcia
30071 Murcia (Spain)
meacacio,joseg,jmgarcia @ditec.um.es
Jos´e Duato
Dpto. Inf. de Sistemas y Computadores
Universidad Polit´ecnica de Valencia
46071 Valencia (Spain)
jduato@gap.upv.es
Abstract
Recent technology improvements allow multiprocessor
designers to put some key components inside the processor
chip, such as the memory controller and the network inter-
face. In this work we exploit such integration scale, present-
ing a new three-level directory architecture aimed at reduc-
ing the long L2 miss latencies and the memory overhead
that characterize cc-NUMA machines and limit their scal-

  

Source: Acacio, Manuel - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia

 

Collections: Computer Technologies and Information Sciences