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Summary: ASSESSING MERGED DRAM/LOGIC 'TECHNOLOGY
Yong-Bin Kim* Tom Chen**
*Engineering Systems Lab. MS-55, Fort Collins, CO 80525
ybk@hpesybk.fc.hp.com
**Department of Electrical Engineering, Colorado State Univ. Fort Collins, CO 80523
chen@longs.lance.colostate.edu
ABSTRACT
This paper describes the impact of DRAM pro-
cess on the logic circuit performance of Memory/Logic
Merged Integrated Circuit and the alternative circuit
design technology to offset the performance penalty.
Three state-of-the-art logic processes(0.5 pm, 0.6pm,
and 0.8pm) and two state-of-the-art DRAM(64Mb and
256Mb) processes have been selected for the study.
The simulation results show that the logic circuit per-
formance is degraded about 22% on DRAM process
including the increased interconnect delay due to less
interconnect layers available in DRAM process. The
silicon area increased up to 80% depending on the
number of net and com onents when implementing a
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