Summary: Appears in IEEE Workshop on VLSI, Orlando, Florida, April 2001
Load-Sensitive Flip-Flop Characterization
Seongmoo Heo and Krste Asanovi´c
Massachusetts Institute of Technology
Laboratory for Computer Science
200 Technology Square, Cambridge, MA 02139, USA
fheomoo,krsteg@mit.edu
Abstract
Different flip-flop designs vary in the number and com-
plexity of logic stages they contain, and hence have different
inherent parasitic delays and output drive strengths. We ex-
amine the effect of electrical load on flip-flop delay and en-
ergy consumption and show that the relative ranking of op-
timized flip-flop structures varies widely with both electrical
effort and absolute load. We also show that some structures
benefit substantially from the addition of appropriate output
buffering.
1. Introduction
Timing elements (TEs), including various forms of flip-
flop and latch, are one of the most important components

Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Asanoviæ, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, SCALE Group

Collections: Computer Technologies and Information Sciences