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Replacing Global Wires with an On-Chip Network: A Power Analysis
 

Summary: Replacing Global Wires with an On-Chip Network:
A Power Analysis
Seongmoo Heo and Krste Asanovi´c
MIT Computer Science and Artificial Intelligence Laboratory
32 Vassar Street, Cambridge, MA 02139
ˇ
heomoo,krste˘ @csail.mit.edu
ABSTRACT
This paper explores the power implications of replacing global chip
wires with an on-chip network. We optimize network links by
varying repeater spacing, link pipelining, and voltage scaling, to
significantly reduce the energy to send a bit across chip. We de-
velop an analytic model of large chip designs with an on-chip two-
dimensional mesh network and estimate the power savings possi-
ble in a 70 nm process for two different design points: a circuit-
switched ASIC or FPGA design, and a dynamic packet-switched
tiled architecture. For circuit-switched networks, achievable power
savings are 35­50% for a mesh with 1 mm links. The packet
switched designs use multiplexing and signal encoding to reduce
the number of link wires required, but the router overhead limits

  

Source: Asanović, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, SCALE Group

 

Collections: Computer Technologies and Information Sciences