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SELECTED FOR IEEE TRANS. ON COMPUTERS, SPECIAL ISSUE ON CACHES, FEB 1999 (NOT THE FINAL VERSION) 1 The Impact of Exploiting InstructionLevel
 

Summary: SELECTED FOR IEEE TRANS. ON COMPUTERS, SPECIAL ISSUE ON CACHES, FEB 1999 (NOT THE FINAL VERSION) 1
The Impact of Exploiting Instruction­Level
Parallelism on Shared­Memory Multiprocessors
Vijay S. Pai, Parthasarathy Ranganathan, Hazim Abdel­Shafi, and Sarita Adve
Department of Electrical and Computer Engineering
Rice University
Houston, Texas 77251­1892
fvijaypai---parthas---shafi---saritag@rice.edu
Abstract--- Current microprocessors incorporate tech­
niques to aggressively exploit instruction­level parallelism
(ILP). This paper evaluates the impact of such processors
on the performance of shared­memory multiprocessors, both
without and with the latency­hiding optimization of soft­
ware prefetching.
Our results show that while ILP techniques substantially
reduce CPU time in multiprocessors, they are less effec­
tive in removing memory stall time. Consequently, despite
the inherent latency tolerance features of ILP processors,
we find memory system performance to be a larger bot­
tleneck and parallel efficiencies to be generally poorer in

  

Source: Adve, Sarita - Department of Computer Science, University of Illinois at Urbana-Champaign

 

Collections: Computer Technologies and Information Sciences