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Limits and Opportunities for Designing Manycore Processor-to-Memory Networks using Monolithic Silicon Photonics
 

Summary: Limits and Opportunities for Designing Manycore Processor-to-Memory Networks
using Monolithic Silicon Photonics
Ajay Joshi*, Christopher Batten, Yong-Jin Kwon, Scott Beamer, Imran Shamim
Krste Asanovi┤c, Vladimir Stojanovi┤c
* Department of ECE, Boston University, Boston, MA
Department of EECS, Massachusetts Institute of Technology, Cambridge, MA
Department of EECS, University of California, Berkeley, CA
1. Introduction
To sustain the historic performance improvement in VLSI
systems, while remaining within the power envelope, the
trend has moved towards designing multiple cores on a sin-
gle die. However, if designed using current and/or pro-
jected electrical solutions, these systems would quickly get
bandwidth-limited due to bandwith density limitations and
power constraints. It is therefore necessary to explore al-
ternate interconnect technologies like silicon photonics that
could provide high bandwidth density and energy-efficient
data transmission. Here, we summarize the results from our
study [1] to determine the limits and opportunities for using
silicon photonic technology for designing core-to-memory

  

Source: AsanoviŠ, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)

 

Collections: Computer Technologies and Information Sciences