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Cache Coherence Protocols for Many-Core CMPs 93 Cache Coherence Protocols for Many-Core CMPs
 

Summary: Cache Coherence Protocols for Many-Core CMPs 93
0
Cache Coherence Protocols for Many-Core CMPs
Alberto Ros, Manuel E. Acacio and Jos´e M. Garc´ia
Universidad de Murcia
Spain
1. Introduction
Multi-core architectures have emerged as the best alternative to take advantage of the increas-
ing number of transistors currently offered in a single die. For example, the dual-core IBM
Power6 (Le et al., 2007) and the eight-core Sun UltraSPARC T2 (Shah et al., 2007) have a rela-
tively small number of cores, which are typically connected through a shared medium, i.e., a
bus or a crossbar. However, CMP architectures that integrate tens of processor cores (usually
known as many-core CMPs) are expected for the near future, after Intel recently unveiled the
80-core Polaris prototype (Azimi et al., 2007). Since the area required by a shared intercon-
nect becomes impractical as the number of cores grows (Kumar et al., 2005), it seems that the
processing cores of future CMPs will be connected by means of unordered point-to-point net-
works. Hence, tiled CMP architectures (Taylor et al., 2002; Zhang & Asanovic, 2005), which
are designed as arrays of replicated tiles connected over a point-to-point network, have arisen
as a scalable alternative to current small-scale CMP designs and they will help in keeping
complexity manageable.

  

Source: Acacio, Manuel - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia

 

Collections: Computer Technologies and Information Sciences