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Model Checking of Hierarchical State Machines RAJEEV ALUR
 

Summary: Model Checking of Hierarchical State Machines
RAJEEV ALUR
University of Pennsylvania and Bell Laboratories
and
MIHALIS YANNAKAKIS
Bell Laboratories
Model checking is emerging as a practical tool for detecting logical errors in early stages of system
design. We investigate the model checking of sequential hierarchical nested systems, i.e., nite-
state machines whose states themselves can be other machines. This nesting ability is common
in various software design methodologies and is available in several commercial modeling tools.
The straightforward way to analyze a hierarchical machine is to atten it thus, incurring an
exponential blow up and apply a model checking tool on the resulting ordinary FSM. We show
that this attening can be avoided. We develop algorithms for verifying linear-time requirements
whose complexity is polynomial in the size of the hierarchical machine. We address also the
veri cation of branching-time requirements and provide e cient algorithms and matching lower
bounds.
Categories and Subject Descriptors: D.2.2 SoftwareEngineering : Design Tools and Techniques|
Object-oriented design methods; state diagrams; D.2.4 SoftwareEngineering : Software Program
Veri cation|formal methods; model checking; F.3.1 Logics and Meanings of Programs :
Specifying and Verifying and Reasoning about Programs|mechanical veri cation; speci cation

  

Source: Alur, Rajeev - Department of Computer and Information Science, University of Pennsylvania

 

Collections: Computer Technologies and Information Sciences