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Micronets: A Model for Decentralising Control in Asynchronous Processor Architectures
 

Summary: Micronets: A Model for Decentralising Control in Asynchronous
Processor Architectures
D. K. Arvind, R. D. Mullins and V. E. F. Rebello
Department of Computer Science, The University of Edinburgh
Edinburgh, EH9 3JZ, United Kingdom
E­mail: dka@dcs.ed.ac.uk
Abstract
Micronets model processor architectures as a net­
work of communicating resources, in contrast to the
traditional one of a linear pipeline. Micronets distrib­
ute the control to the functional units, which enables
the exploitation of fine­grain concurrency between in­
structions. The overhead due to asynchrony is hid­
den with the four­phase protocol being used to imple­
ment scoreboarding and hazard avoidance mechanisms,
without incurring additional control costs. This pa­
per demonstrates the feasibility of micronet­based pro­
cessors. Results are presented for SPICE­level simula­
tions of a 0.7¯m CMOS implementation of a datapath.
The relationships between micronets and both the com­

  

Source: Arvind, D. K. - School of Informatics, University of Edinburgh

 

Collections: Computer Technologies and Information Sciences