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Chip Multi-Processor Scalability for Single-Threaded Applications Neil Vachharajani
 

Summary: Chip Multi-Processor Scalability for Single-Threaded Applications
Neil Vachharajani
, Matthew Iyer
, Chinmay Ashok
Manish Vachharajani
, David I. August
, and Daniel Connors
Department of Computer Science Department of Electrical and Computer Engineering
Princeton University University of Colorado at Boulder
{nvachhar,august}@princeton.edu {iyer, ashokc, manishv, dconnors}@colorado.edu
Abstract
The exponential increase in uniprocessor performance
has begun to slow. Designers have been unable to scale
performance while managing thermal, power, and electri-
cal effects. Furthermore, design complexity limits the size
of monolithic processors that can be designed while keep-
ing costs reasonable. Industry has responded by moving
toward chip multi-processor architectures (CMP). These
architectures are composed from replicated processors
utilizing the die area afforded by newer design processes.

  

Source: August, David - Department of Computer Science, Princeton University

 

Collections: Computer Technologies and Information Sciences