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Low-Power Reconfigurable VLSI Architecture for the Implementation of FIR Filters

Summary: Low-Power Reconfigurable VLSI Architecture for the Implementation
of FIR Filters
Evangelos F. Stefatos, Han Wei, Tughrul Arslan, Robert Thomson
School of Engineering & Electronics
The University of Edinburgh, King's Buildings, Mayfield Rd, Edinburgh, EH9 3JL,
Scotland, UK
{Evangelos.Stefatos, W.Han, Tughrul.Arslan, Robert.Thomson}@ee.ed.ac.uk
This paper presents a custom reconfigurable VLSI
architecture that is tailored for the implementation of
low-power, medium/high order, digital finite impulse
response (FIR) filters. These are realized within a
reconfigurable array that consists of heterogeneous,
programmable, arithmetic-logic units. The reconfigurable
design is based on the primitive operator design (POF)
technique. The concept of a genetic algorithm (GA) is
introduced, which utilizes a randix-4, 256-point fast-
fourier-transform (FFT) to calculate the frequency
response of the evolved filters. The results related to the
performance, physical-area and power consumption make


Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh


Collections: Engineering