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A Low Power Heterogenous Reconfigurable Architecture For Embedded Generic Finite State Machines
 

Summary: A Low Power Heterogenous Reconfigurable Architecture For
Embedded Generic Finite State Machines
Zhenyu Liu1, Tughrul Arslan"2, Sami Khawaml, Ahmet T. Erdogan'2
1 School of Engineering and Electronic, The University of Edinburgh, King's Buildings,
Mayfield Road, Edinburgh EH9 3JL, UK.
2 Institute for System Level Integration, Livingston, EH54 7EG, UK
zhenyu.liueed.ac.uk
ABSTRACT
Domain-specific reconfigurable arrays are
usually designed for specific applications and
provide a good compromise between speed, power
and flexibility. In this paper, a novel reconfigurable
Finite State Machine (FSM) array is presented for
implementing generic FSMs. Compared with
commercial FPGA devices, the new architecture
provides the following reductions: up to 90% in
power consumption, up to 55% in area and around
20% in delay time.
1. INTRODUCTION
Reconfigurable System-on-Chip (SoC)

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering