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Minimizing Sensitivity to Clock Skew Variations Using Level Sensitive Latches
 

Summary: Minimizing Sensitivity to Clock Skew Variations
Using Level Sensitive Latches
François-R. Boyer*, El Mostapha Aboulhamid*, and Yvon Savaria
Abstract -- We propose a method for improving the toler-
ance of synchronous circuits to delay variations on the
clock distribution. Instead of retiming and clock skew
scheduling applied to edge-triggered flip-flops, as used by
most other methods, we use level-sensitive latches placed
based on a schedule of the operations. The resulting cir-
cuit can have a non-zero tolerance even at the optimal
clock period, which is impossible with edge-triggered flip-
flops.
1 Introduction
As clock frequencies get higher and the clock distribu-
tion network gets larger, the fluctuation on the arrival
time of the clock signals gets important compared to
the clock period. Clock distribution networks can be
made more precise [4], but they are not perfect. For a
circuit to work properly at high speed, it must be de-
signed to have tolerance to delay fluctuations.

  

Source: Aboulhamid, El Mostapha - Département d'Informatique et recherche opérationnelle, Université de Montréal
Boyer, Francois. R . - Département de Génie Informatique, École Polytechnique de Montréal

 

Collections: Computer Technologies and Information Sciences; Engineering