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Proceedings of the 5th International Symposium on High Performance Computer Architecture, January 1999. Supporting FineGrained Synchronization on a Simultaneous Multithreading Processor
 

Summary: Proceedings of the 5th International Symposium on High Performance Computer Architecture, January 1999.
Supporting Fine­Grained Synchronization on a Simultaneous Multithreading Processor
Dean M. Tullsen
Dept. of Computer Science and Engineering
University of California, San Diego
tullsen@cs.ucsd.edu
Jack L. Lo
Transmeta Corporation
Santa Clara, CA
jlo@transmeta.com
Susan J. Eggers, Henry M. Levy
Dept. of Computer Science and Engineering
University of Washington
feggers,levyg@cs.washington.edu
Abstract
This paper proposes and evaluates new synchronization
schemes for a simultaneous multithreaded processor. We
present a scalable mechanism that permits threads to cheaply
synchronize within the processor, with blocked threads con­
suming no processor resources. We also introduce the concept

  

Source: Anderson, Richard - Department of Computer Science and Engineering, University of Washington at Seattle
Wang, Deli - Department of Electrical and Computer Engineering, University of California at San Diego

 

Collections: Computer Technologies and Information Sciences; Engineering; Materials Science