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Summary: GLOBAL INSTRUCTION SCHEDULING FOR
MULTI-THREADED ARCHITECTURES
GUILHERME DE LIMA OTTONI
A DISSERTATION
PRESENTED TO THE FACULTY
OF PRINCETON UNIVERSITY
IN CANDIDACY FOR THE DEGREE
OF DOCTOR OF PHILOSOPHY
RECOMMENDED FOR ACCEPTANCE
BY THE DEPARTMENT OF
COMPUTER SCIENCE
ADVISOR: DAVID I. AUGUST
SEPTEMBER 2008
c Copyright by Guilherme de Lima Ottoni, 2008.
All Rights Reserved
Abstract
Recently, the microprocessor industry has moved toward multi-core or chip multipro-
cessor (CMP) designs as a means of utilizing the increasing transistor counts in the face
of physical and micro-architectural limitations. Despite this move, CMPs do not directly
improve the performance of single-threaded codes, a characteristic of most applications. In
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