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Figure 1 Schematic of the proposed comparator [6] Offset Voltage Analysis of Dynamic Latched
 

Summary: Figure 1 Schematic of the proposed comparator [6]
Offset Voltage Analysis of Dynamic Latched
Comparator
HeungJun Jeon and Yong-Bin Kim
Department of Electrical and Computer Engineering
Northeastern University
Boston, MA, USA
hjeon@ece.neu.edu, ybk@ece.neu.edu
Abstract-- In this paper, the proposed dynamic latched
comparator, which has a separated dynamic differential input
gain stage and output stage combined with a latch, is analyzed.
A method to estimate the input-referred offset voltage and to
maximize the gain of the dynamic pre-amplifier is presented.
The difference between the HSPICE and the estimated input-
referred offset voltage using the proposed approach turns out
to be within 12% range.
I. INTRODUCTION
Dynamic latched comparators are used for many
applications such as high-speed analog-to-digital converters
(ADCs), memory sense amplifiers (SAs), and data receivers

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering