Synthesis of Interface Controllers from Timing Diagram
Abdelhalim El-Aboudi, El-Mostapha Aboulhamid, Eduard Cerny
Labratoire LASSO, Département IRO, Université de Montréal
Montréal (Québec) CANADA
We present a method for verifying the realizability of a timing
diagram, ensuring the synthesis of the underlying interface is
possible. If necessary, a heuristic is introduced to render
explicit hidden timing constraints implied by the specification.
A relative schedule of output events is computed, accepting
input events from the complete timing space defined by the
assumed constraints on the environment.
Timing diagrams, timing constraints, realizability, relative
Interface design is an important aspect of the design of digital
microelectronic systems. This importance is growing with the