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MULTIPLIER-LESS BASED PARALLEL-PIPELINED FFT ARCHITECTURES FOR WIRELESS COMMUNICATION APPLICATIONS
 

Summary: MULTIPLIER-LESS BASED PARALLEL-PIPELINED FFT ARCHITECTURES FOR
WIRELESS COMMUNICATION APPLICATIONS
Wei Han, T. Arslan, A. T. Erdogan and M. Hasan
School of Engineering and Electronics, University of Edinburgh, Edinburgh, UK.
ABSTRACT
This paper proposes two novel parallel-pipelined FFT architec-
tures based on multiplier-less implementation targeting wireless
communication applications, such as IEEE 802.11 wireless base-
band chip and MC-CDMA receiver. The proposed parallel-
pipelined architectures have the advantages of high throughput and
high power efficiency. The multiplier-less architecture uses shift
and addition operations to realize complex multiplications. By
combining a new commutator architecture, and a low power butter-
fly with this approach, the resulting power and area savings are up
to 31% and 20% respectively, for 64-point and 16-point FFTs, as
compared to parallel-pipelined FFTs based on Booth coded Wal-
lace tree multipliers.
1. INTRODUCTION
The FFT processor is widely used in DSP and communication ap-
plications. It is a critical block in OFDM based communication

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering