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VHDL'92 8.1 Language Change Specifications
 

Summary: VHDL'92 8.1
SESSION 8
VHDL'92
Language Change Specifications
VHDL'92 8.2
Declarative part in generate statements
LCS-0001(3)
Solution
generate_label :
generation_scheme GENERATE
[ { block_declarative_item } -- optional declarative part
BEGIN ]
{ concurrent_statement }
END GENERATE [generate_label ] ;
Problem
· Generate statement constitutes a declarative region.
· Configuration specifications for component instantiations nested immediately
inside generate statements is a problem.
· Component instantiation statements must be enclosed in an artificial block
statement in order to have a declarative part in which to place the configuration

  

Source: Aboulhamid, El Mostapha - Département d'Informatique et recherche opérationnelle, Université de Montréal

 

Collections: Engineering