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A High Performance Synthesisable Unsymmetrical Reconfigurable Fabric For Heterogeneous Finite State Machines
 

Summary: A High Performance Synthesisable Unsymmetrical Reconfigurable Fabric
For Heterogeneous Finite State Machines
Zhenyu Liu1
, Tughrul Arslan1,2
, Sami Khawam1
, Iain.Lindsay
1 School of Engineering and Electronic, The University of Edinburgh, King's Buildings,
Mayfield Road, Edinburgh EH9 3JL, UK.
2 Institute for System Level Integration, Livingston, EH54 7EG, UK
{zhenyu.liu, Tughrul.Arslan, S.Khawam, Iain.Lindsay} @ee.ed.ac.uk
Abstract - The use of synthesizable reconfigurable cores in
system on chip (SoC) designs is increasingly becoming a trend.
Such domain-special cores are being used for their flexibility,
powerful function and low power consumption. A
reconfigurable Finite State Machine (FSM) is constantly
required for the purpose of control in any reconfigurable SoC.
This paper presents a novel unbalanced unsymmetrical
reconfigurable architecture for generic FSM; Compared with
commercial FPGA devices, the new architecture results in area
reduction of 43% and power consumption decrease of 82%.

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering