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Summary: Abstract
With increasing clock frequencies and silicon integration,
power aware computing has become a critical concern in the design
of embedded processors and systems-on-chip. One of the more effec-
tive and widely used methods for power-aware computing is
dynamic voltage scaling (DVS). In order to obtain the maximum
power savings from DVS, it is essential to scale the supply voltage as
low as possible while ensuring correct operation of the processor.
The critical voltage is chosen such that under a worst-case scenario
of process and environmental variations, the processor always oper-
ates correctly. However, this approach leads to a very conservative
supply voltage since such a worst-case combination of different vari-
abilities will be very rare. In this paper, we propose a new approach
to DVS, called Razor, based on dynamic detection and correction of
circuit timing errors. The key idea of Razor is to tune the supply volt-
age by monitoring the error rate during circuit operation, thereby
eliminating the need for voltage margins and exploiting the data
dependence of circuit delay. A Razor flip-flop is introduced that dou-
ble-samples pipeline stage values, once with a fast clock and again
with a time-borrowing delayed clock. A metastability-tolerant com-
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