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A Novel 8-Phase PLL Design for PWM Scheme in High Speed I/O Circuits
 

Summary: A Novel 8-Phase PLL Design for PWM Scheme in
High Speed I/O Circuits
Rui Tang, Yong-Bin Kim
Northeastern University
360 Huntington Ave. Boston, MA, USA 02115
rtang@ece.neu.edu, ybk@ece.neu.edu
ABSTRACT
A novel phase-locked-loop (PLL) topology for
pulse width modulation (PWM) technique in high
speed I/O circuits is presented in this paper. The
VCO of the PLL generates the eight phase clocks
of the same frequency. A simple level shifter
structure is used to amplify the VCO output signal
to the full voltage swing and guarantee 50% duty
cycle for a wide range of frequency. The
performance of the charge-pump and phase-
frequency detector is improved from the previous
research. The proposed PLL can be used in both
transmitter end and receiver end and the
performance satisfies the requirements of high

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering