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Timed Automata Rajeev Alur
 

Summary: Timed Automata
Rajeev Alur
University of Pennsylvania and Bell Labs
alur@cis.upenn.edu
Abstract
Model checking is emerging as a practical tool for automated debugging of complex reactive systems
such as embedded controllers and network protocols (see [CK96] for a survey). In model checking, a
high­level description of a system is compared against a logical correctness requirement to discover
inconsistencies. Traditional techniques for model checking do not admit an explicit modeling of
time, and are thus, unsuitable for analysis of real­time systems whose correctness depends on
relative magnitudes of different delays. Consequently, timed automata [AD94] were introduced as
a formal notation to model the behavior of real­time systems. Its definition provides a simple, and
yet general, way to annotate state­transition graphs with timing constraints using finitely many
real­valued clock variables . Automated analysis of timed automata relies on the construction of
a finite quotient of the infinite space of clock valuations. Over the years, the formalism has been
extensively studied leading to many results establishing connections to circuits and logic, and much
progress has been made in developing verification algorithms, heuristics, and tools. This paper
provides a survey of theory of timed automata, and their role in specification and verification of
real­time systems.
1 Modeling

  

Source: Alur, Rajeev - Department of Computer and Information Science, University of Pennsylvania

 

Collections: Computer Technologies and Information Sciences