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Probabilistic Leakage Power Estimation of Partially-Depleted Silicon-On-Insulator (SOI) Gates
 

Summary: Probabilistic Leakage Power Estimation of
Partially-Depleted Silicon-On-Insulator (SOI) Gates
Kyung Ki Kim, and Yong-Bin Kim
Department of Electrical and Computer Engineering
Northeastern University
Boston, MA 02115, USA
Email: {kkkim, ybk}@ece.neu.edu
Abstract-- This paper presents a novel probability based analy-
sis for leakage power estimation of Partially-Depleted Silicon-
On-Insulator (PD-SOI) circuits. The proposed leakage power
estimation algorithms is implemented in C language, and the
proposed methodology is tested by ISCAS85 benchmark circuits
designed in 100nm SOI technology. The results show that the
error is within 4% compared with Hspice Monte Carlo simulation
results.
I. INTRODUCTION
Partially-Depleted Silicon-On-Insulator (PD-SOI) has been
advocated as a substitute for conventional silicon technology.
It has been demonstrated that a SOI transistor offers high per-
formance, dense integration, and reduced power consumption

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering