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To appear in the Journal of Parallel and Distributed Computing, 1992 Programming for Different Memory Consistency Models **
 

Summary: ­­ ­­
To appear in the Journal of Parallel and Distributed Computing, 1992
Programming for Different Memory Consistency Models **
Kourosh Gharachorloo + , Sarita V. Adve # ,
Anoop Gupta + , John L. Hennessy + , and Mark D. Hill #
+ Computer System Laboratory
Stanford University
Stanford, California 94305
# Computer Sciences Department
University of Wisconsin
Madison, Wisconsin 53706
ABSTRACT
The memory consistency model, or memory model, supported by a shared­memory multiprocessor directly
affects its performance. The most commonly assumed memory model is sequential consistency (SC). While SC
provides a simple model for the programmer, it imposes rigid constraints on the ordering of memory accesses and
restricts the use of common hardware and compiler optimizations. To remedy the shortcomings of SC, several
relaxed memory models have been proposed in the literature. These include processor consistency (PC), weak
ordering (WO), release consistency (RCsc/RCpc), total store ordering (TSO), and partial store ordering (PSO).
While the relaxed models provide the potential for higher performance, they present a more complex model for
programmers when compared to SC.

  

Source: Adve, Sarita - Department of Computer Science, University of Illinois at Urbana-Champaign

 

Collections: Computer Technologies and Information Sciences