Boolean functions are fundamental to synthesis and veri-
fication of digital logic, and compact representations of
Boolean functions have great practical significance. Popu-
lar representations, such as CNF, DNF, circuits and ROB-
DDs , offer different advantages and are preferred for
different tasks. Conversion between those representations is
common, especially when one is used to represent the input
and another speeds up relevant algorithms.
Our work addresses the construction of ROBDDs that rep-
resent outputs of a given Boolean circuit. It is used in synthe-
sis and verification . Earlier works [7, 10] proposed
ordering circuit inputs and gates by graph traversals. We
contribute orderings based on circuit partitioning and
placement, leveraging the progress in recursive bisection
and multi-level min-cut partitioning achieved in late 1990s.
Our empirical results show that the proposed orderings
based on circuit partitioning and placement are more suc-
cessful than straightforward DFS and BFS, as well as rela-
ted heuristics proposed in [7, 10, 12].